As shown, for example, in the drawing at page 32 of “SANYO TECHNICAL REVIEW” Vol. 10, No. 1, February 1978, a PLL circuit that generates signals of various frequencies from a reference signal having a certain frequency is known. This PLL circuit includes a reference oscillator generating a reference signal RF, a voltage-controlled oscillator generating an output signal FO having a frequency responsive to a control voltage CV, a variable frequency divider dividing the frequency of the output signal FO to generate a feedback signal FV, a phase comparator comparing phases between the feedback signal and the reference signal to generate an error signal ER, and a low-pass filter generating the control signal CV in response to the error signal ER.
However, this PLL circuit has disadvantage of having a long lock-up time (the time until the output signal is synchronized with the reference signal) since its phase comparator is of the single-stage type that performs the phase comparison only once during one period of the reference signal.
There are some PLL circuits that are free from the disadvantage of the long lock-up time. For example, each of Japanese Unexamined Patent Publication 10-135822 and Japanese Unexamined Patent Publication 11-20405 by the inventor identical with the inventor of the present invention discloses a PLL circuit that performs phase comparisons multiple times during one period of the reference signal to shorten the lock-up time.
The PLL circuit disclosed in Japanese Unexamined Patent Publication 10-135822 includes means for generating a plurality of reference signals having mutually differing phases, a plurality of (four, for example) frequency dividers each dividing an output signal of a voltage-controlled oscillator, a plurality of phase comparators each comparing phases between output signals of the frequency dividers and the corresponding reference signals, a plurality of gates disposed at the inputs of the frequency dividers, etc., and performs phase comparisons multiple times during one period of the reference signal to shorten the lock-up time.
However, this PLL circuit consumes large electricity since it has a plurality of (four) frequency dividers. To perform phase comparisons eight times during one period of the reference signal so that the lock-up time is further shortened, eight frequency dividers are required, which increases the power consumption downhill. In addition, there is a problem that the PLL circuit is large in dimension, costly, and difficult to implement in an LSI, since it has a plurality of frequency dividers and a plurality of phase comparators each of which requires a relatively large layout space.
The PLL circuit disclosed in Japanese Unexamined Patent Publication 11-20405 includes a reference oscillator, a fixed frequency divider dividing an output of the reference oscillator, a reference signal generating means for dividing an output of the fixed frequency divider to generate a plurality of reference signals having mutually differing phases, a voltage-controlled oscillator, a plurality of variable frequency dividers each dividing an output of the voltage-controlled oscillator, a plurality of phase comparators comparing phases between the reference signals and outputs of the variable frequency dividers.
In this PLL circuit, the frequency of the reference signals supplied to the phase comparators must match a channel spacing frequency, or a frequency spacing of the signals to be produced by this PLL circuit. For example, in a case where this PLL circuit has four phase comparators and four variable frequency dividers when the oscillation frequency of the reference oscillator is 13 MHz and the channel spacing frequency is 200 kHz, the fixed frequency divider must supply the reference signal generating means with a signal having a frequency of 200 kHz×4=800 kHz, since the frequency of the reference signals supplied to the phase comparators should be 200 kHz. That is, in this case, the frequency-division ratio of the fixed frequency divider has to be 13 MHz/800 kHz=16.25 (=16+1/4 ). It is difficult to manufacture such a frequency divider having a frequency-division ratio that includes a decimal fraction of 1/4, and will be extremely expensive even if it is manufactured.
As described above, the PLL circuit disclosed in Japanese Unexamined Patent Publication 11-20405 has, in addition to the disadvantage of the PLL circuit disclosed in Japanese Unexamined Patent Publication 10-135822, the disadvantage that it is difficult to adapt to many and various reference oscillators and channel spacing frequencies.
A first object of the present invention is to provide a PLL circuit which has a short lock-up time and a small electric power consumption, is easy to implement in an LSI, and is low in manufacturing cost.
A second object of the present invention is to provide a PLL circuit which has a short lock-up time and a small electric power consumption, is easy to implement in an LSI, and is adaptable to any reference oscillator and channel spacing frequency.